Verilog Behavioral Simulation version 1.2.0

	This is the public distribution of the Verilog Behavioral
Simulator.  Verilog is a Hardware Description Language used mostly for
digital circuit design and simulation.  This program is a simple
implementation of a Verilog simulator, supporting only synthesizable
behavioral constructs.  This program was developed for the senior design
project in the electrical engineering curriculum of the University of
Hawaii, College of Engineering. 


What's New?

	This release adds support for scope resolution in the symbol
table, module instantiation, and user defined functions & tasks.  There
are also extensive code updates and bug fixes.  A special note for this
release.  There is now a requirement that the top level module for the
test vector must be named "main".  See the change log and documentations
for details.  The "Supported" document has a list of other limitations.
Please read it before using the simulator. 


Contents

This distribution contains the source code to the Verilog Behavioral 
Simulator.  This directory contains the following subdirectories and files:

COPYING-2.0
Copyright	Copyright conditions.
Todo		File containing todo list.  Also has a list of limitations. 
ChangeLog	Log of changes to the base code.
src/		Unarchived directory of latest working version.
data/		Example verilog code to test the program.
tests/		Directory containing test programs for objects.
docs/		Directory of documentation.
prjdata/	Text files from the senior design project.


Getting the source code:

Source code to this project can be obtained from the Verilog archive site
on the world wide web.  The URL is:

http://www.cray.com/verilog/archive.html
ftp://ftp.cray.com/pub/comp.lang.verilog/vbs-X.X.tar.gz

The authors do not maintain this site, so the location could change without
notice.


To Create the Program:

This software requires the following to compile:
	flex 2.3 or later
		Or any POSIX lex which can generate ANSI C code.  (*) (**)
	bison 1.22 or later
		POSIX yacc should work too.  Must be able to create the
		header file 'yy.tab.h', as well as ANSI C code.  (**)
	Any ANSI C compiler
		We used gcc 2.6.3.
	C++ compiler that supports templates.
		We used g++ 2.6.3.  Earlier versions did not handle
		templates correctly.

(*)  If you use flex 2.3, you might need to undefine 'yywrap'.  Version
2.3 has this word defined rather than a function in the library. 

(**)  We use both ANSI and POSIX standards.  Thus, if turning on ANSI with
your C or C++ compiler breaks the POSIX code, do not turn on ANSI.  This
is the case for GCC.  Turning on ANSI (-ansi) will turn off POSIX.

1.  Change directory into the 'src' directory.
2.  Type 'make vbs'.  An executable 'vbs' will be generated.  (*)
3.  Run the program on example files by typing 'vbs ../data/testfiles.v'
	(where 'testfiles' are one of the premade tests).  (**)

(*)  If you receive any warnings about "defined but not used" or
"assignment between integer and pointer", ignore these.  They are problems
with the system files, not this package. 

(**)  The output of the executable can contain a few debug statements for
easier analysis.  See the Makefile for a list of debug defines, and what
they do. 


Testing individual C++ objects:

1.  Change directory into the 'src' directory
2.  Type 'make' to get a list of targets.
3.  Type 'make target' to test that object.

Note:  the test modules do not test every conceivable permutation of usage
for the C++ classes.  Only basic, or required, methods (member functions)
are tested, because we need to use them. 


As usual, this program has only been tested on a Linux system.  If you
find any problems, or have questions and comments, please send them to:

jching@aloha.com

If you wish to help develop this simulator, please also drop me a note.
Further work is in progress.  But due to other engagements, only bug
fixes will be done by the authors until further notice.
