Todo List
6/10/95

This is a list of features that are lacking in the current implementation
of the Verilog Behavioral simulator.  This list is sorted according to
priority.

1.  Fix bugs.
	Delays in nested blocks still does not work in 'for' loops.  It
	might take some time to fix this one.

	There are no other known bugs at the moment.  But we are sure they
	exist.  Most of the bugs found were in the BitVector implementation.
	So we suggest looking there first.  If an 'internal simulator error'
	message comes up, the problem is most likely in the symbol table.

2.  Better error reporting.
	Right now, the lex scanner and yacc parser does not provide good error
	reporting or error recovery.  Lex and yacc already have error reporting
	features.  So adding this should be easy.

3.  Use standard tools.
	At the moment, the source code is not very clean in terms of being
	standard.  One of the goal of this project is to have this program
	run on many platforms.  So conforming to POSIX and ANSI C/C++ is a
	plus.

4.  Add logfile support.
	Decide what should be logged and where in the code to log it.
	Including sanity checks in all objects seems too paranoid.  But
	if we are to support a logfile, this is basically what we need
	to do.  The best way to do this is to start at the highest
	level in the object hierarchy.
	(Sanity check: have the object tell us what it is doing.)

5.  Add preprossesing support.
	Does this require writing a seperate preprocessor?

6.  Add memory support.
	I believe this only requires a new symbol table type.

7.  Lots of memory leaks.
	Try to find all memory leaks and remove them.

8.  Reduce code bloat.
	This might be caused by all the inlined constructors.

These are only a few suggestions for enhancement.  It will take some time
to add all these features.  We might also have missed other Verilog
constructs that are important.  If so, they should have higher priority.

Lay Hoon Tho
Jimen Ching
